Title :
Systematic design approach of Mastrovito multipliers over GF(2m)
Author :
Zhang, Tong ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
This paper considers the design of low-complexity bit-parallel dedicated finite field multiplier. A systematic design approach of Mastrovito (1988) multiplier is proposed, which is applicable to GF(2 m) generated by an arbitrary irreducible polynomial. This approach extensively exploits the spatial correlation of matrix elements in Mastrovito multiplication to reduce the complexity. The developed general Mastrovito multiplier is highly modular, which is desirable for VLSI hardware implementation. Meanwhile, the presented approach can be used to develop efficient Mastrovito multipliers for several special irreducible polynomials, such as a trinomial and equally-spaced-polynomial, and further find some other special irreducible polynomials which can also lead to low-complexity multipliers
Keywords :
Galois fields; Toeplitz matrices; VLSI; computational complexity; correlation methods; multiplying circuits; polynomials; Mastrovito multiplication; Mastrovito multipliers; Toeplitz matrix; VLSI hardware implementation; bit-parallel finite field multiplier; equally-spaced-polynomial; irreducible polynomial; low-complexity multiplier; matrix elements; modular multiplier; spatial correlation; systematic design; trinomial; Algorithm design and analysis; Application software; Computer architecture; Computer errors; Cryptography; Electrostatic precipitators; Galois fields; Hardware; Polynomials; Very large scale integration;
Conference_Titel :
Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-6488-0
DOI :
10.1109/SIPS.2000.886749