Fine-grain asynchronous circuits for low-power high performance DSP implementations

The aim of this paper is to present a new approach to creating low-power high-performance DSP using delay-insensitive asynchronous circuits. To attain this, we pipeline the asynchronous circuit at logic gate level in such a way that every functional unit can be pipelined in many stages, up to as many as half the number of gate levels. Also, we want to integrate this approach with the traditional method to synthesise synchronous circuits. In order to achieve this, we create a new library of gates which satisfy the constraints that asynchronous design requires. Finally, we present the results after building a pipelined multiplier with both synchronous and asynchronous approaches,