A pragmatic test pattern generation system for scan-designed circuits with logic value constraints

In testing for practical logic circuits, there may exist logic value constraints on some part of logic circuits owing to various requirements on design and test. The inefficiency in handling the logic value constraints during the line justification stage of test generation may result in low fault coverage as well as excessive computer time with numerous fruitless searches. This paper presents a logic value system called taboo logic value to represent the logic value constraints and to identify additional logic value constraints using a taboo logic calculus. Also, a test pattern generation algorithm is discussed to show how the taboo logic system can be incorporated into existing test generation algorithms. Finally, experimental results demonstrate the efficiency of the taboo logic values