A novel ESD protection device structure for HV-MOS ICs

A novel npn lateral bipolar ESD protection device structure is proposed for 16 V drain-extended MOS (DEMOS) ICs. This device features a shallow n⁺ ballast region between the n- drift region and the n⁺⁺ drain region. Due to this ballast region, avalanche generation occurs both in this ballast region and in the drain region. This distributed avalanche generation reduces current crowding at the drain edge by splitting the current flowline into two. Consequently, this device suppresses soft leakage degradation and provides excellent linearity of a second breakdown current (I_t2) and of failure voltages in Machine Model (MM)/Human Body Model (HBM) testing to a total gate width ranging from 100 mum to 960 mum. This device provides an I_t2 of up to 11 mA/mum as well. To our knowledge, this is the first report of a high-voltage lateral bipolar protection device without an n⁺ buried layer (NBL) to offer such design and performance qualities. In addition, this device can be fabricated without extra masks or process steps by applying process steps for a low-voltage CMOS IC embedded in a high-voltage (HV)-MOS IC wafer. Therefore, this device is expected to improve the reliability of HV-MOS ICs with minimum additional cost.