Software upset analysis: A case study of the HS1602 microprocessor

This paper describes a simulation based approach to quantify the impact of low-level transient errors at the software execution level. Automated analysis, for the run-time injection of transients at the device level and the assessment of the resulting impact on the program-control flow, is described. Using test workloads, the type of upsets at the program-flow level which can result from fault injection are determined. The methodology is illustrated by a case study of a microprocessor, used in the jet-engine controller of Boeing 747 and 757 aircrafts. For each section in the test program, the chance of having single and multiple upsets from the fault injection is determined. The analysis showed that about 20% of all upsets are multiple in nature. The result suggests that current methods of validation that assume single upsets may be inadequate