Title :
Area estimation for DSP algorithms
Author :
Elleithy, Khaled M. ; Amin, Alaa A.
Author_Institution :
Dept. of Comput. Sci. & Eng., Bridgeport Univ., CT, USA
Abstract :
In this paper we present a method to estimate the layout area of DSP algorithms that are designed using the standard cell methodology. The circuit description is given as a netlist of standard cell library modules. The area occupied by the circuit can be estimated prior to the actual layout phase. Area estimation before final layout is important for design evaluation and for the prediction of the chip floorplan
Keywords :
circuit layout CAD; digital signal processing chips; DSP algorithms; chip floorplan; design evaluation; layout area; standard cell library modules; standard cell methodology; Algorithm design and analysis; Analytical models; Circuits; DH-HEMTs; Digital signal processing; Lattices; Predictive models; Stochastic processes; Wire; Wiring;
Conference_Titel :
Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-6488-0
DOI :
10.1109/SIPS.2000.886760
