Title :
PLANE: A new ATPG system for PLAs
Author :
Huang, Juinn-Dar ; Shen, Wen-Zen
Author_Institution :
Dept. of Electron. Eng., National Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this paper, a new PLA ATPG system PLANE is presented. PLANE uses the depth-first sharp operation for efficient test generation. Besides, a powerful test compaction technique using the intersection buffer is applied to get a more compact test set. PLANE also uses parallel fault simulation and backend fault simulation to exploit its performance. Experimental results show that the test length of PLANE is 7.5% shorter than that of PLATYPUS
Keywords :
automatic test software; digital simulation; fault diagnosis; fault location; logic testing; programmable logic arrays; ATPG; PLA; PLANE; PLATYPUS; backend fault simulation; depth-first sharp operation; intersection buffer; parallel fault simulation; test generation; Automatic test pattern generation; Automatic testing; Boolean functions; Circuit faults; Circuit testing; Compaction; Design for testability; Hardware; Logic circuits; Programmable logic arrays;
Conference_Titel :
Test Symposium, 1993., Proceedings of the Second Asian
Conference_Location :
Beijing
Print_ISBN :
0-8186-3930-X
DOI :
10.1109/ATS.1993.398788
