Title :
Optimization of deterministic test sets using an estimation of product quality
Author :
Spiegel, Gerald ; Stroele, Albrecht P.
Author_Institution :
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
Abstract :
The probabilities of faults in VLSI circuits generally differ by order of magnitude. This paper presents an approach to product quality estimation that considers these different fault probabilities. Two efficient algorithms are described that optimize deterministic test sets such that a high product quality is achieved with short test lengths
Keywords :
VLSI; automatic testing; deterministic algorithms; fault diagnosis; fault location; integrated circuit testing; integrated circuit yield; optimisation; production testing; VLSI circuits; algorithms; deterministic test sets; estimation; optimisation; probabilities; product quality; product quality estimation; Circuit faults; Circuit testing; Fault tolerance; Integrated circuit layout; Partial response channels; Probability; Statistics; Topology; Very large scale integration; Yield estimation;
Conference_Titel :
Test Symposium, 1993., Proceedings of the Second Asian
Conference_Location :
Beijing
Print_ISBN :
0-8186-3930-X
DOI :
10.1109/ATS.1993.398790
