• DocumentCode
    2671824
  • Title

    On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--

  • Author

    Iguchi, Yukihiro ; Sasao, XTsutomu ; Matsuura, Munehiro

  • Author_Institution
    Dept. of Comput. Sci., Meiji Univ., Kawasaki
  • fYear
    2007
  • fDate
    13-16 May 2007
  • Firstpage
    32
  • Lastpage
    32
  • Abstract
    In digital signal processing, radixes other than two are often used for high-speed computation. In the computation for finance, decimal numbers are used instead of binary numbers. In such cases, radix converters are necessary. This paper considers design methods for binary to q-nary converters. It introduces a new design technique based on weighted-sum (WS) functions. The method computes a WS function for each digit by an LUT cascade and a binary adder, then adds adjacent digits with q-nary adders. A 16-bit binary to decimal converter is designed to show the method.
  • Keywords
    adders; digital arithmetic; signal processing; LUT cascade; arithmetic decompositions; binary adder; binary-to-decimal converters; binary-to-q-nary converters; digital signal processing; radix converters; weighted-sum functions; Computer science; Design methodology; Digital arithmetic; Digital signal processing; Digital systems; Finance; Logic; Read only memory; Signal design; Table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic, 2007. ISMVL 2007. 37th International Symposium on
  • Conference_Location
    Oslo
  • ISSN
    0195-623X
  • Print_ISBN
    0-7695-2831-7
  • Type

    conf

  • DOI
    10.1109/ISMVL.2007.39
  • Filename
    4215955