Dual-gate SOI CMOS technology by local overgrowth (LOG)

Summary form only given. A dual-gate CMOS process with excellent device performance is discussed. The low parasitics of SOI devices can be obtained without the penalty of degraded channel mobility that is often observed in zone melting recrystallized (ZMR) material. Low mask count, reduced diffusion times compared to bulk CMOS processing, and excellent planarity enable further stacking or multilayer metallization. Interconnect complexity is greatly simplified by vertical vias to the substrate, providing one power bus. The process gets simpler as device dimensions are scaled down