A global BIST methodology

Author

Gheewala, T. ; Sucar, H. ; Varma, P.

Author_Institution

CrossCheck Technology, Inc., San Jose, CA, USA

fYear

1993

fDate

16-18 Nov 1993

Firstpage

154

Lastpage

159

Abstract

This paper presents a BIST methodology for CMOS gate-arrays. This BIST method involves the extension of a design-independent embedded grid-based test technology that is provided in the base of the gate array to provide an automatic and complete self-test. The use of globally shared test electronics minimizes the area overhead required, while the massive observability of internal circuit nodes afforded by an embedded grid allows high fault coverage of both stuck-at and manufacturing defects, such as shorts and opens, to be achieved

Keywords

CMOS integrated circuits; built-in self test; integrated logic circuits; logic arrays; logic testing; observability; production testing; CMOS gate-arrays; area overhead; automatic test; boundary control; embedded grid; embedded grid-based test technology; fault coverage; global BIST; internal circuit nodes; manufacturing defects; observability; opens; self-test; shorts; stuck at defects; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Electronic equipment testing; Integrated circuit testing; Logic testing; Sequential analysis; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1993., Proceedings of the Second Asian

Conference_Location

Beijing

Print_ISBN

0-8186-3930-X

Type

conf

DOI

10.1109/ATS.1993.398795

Filename

398795