A current testing for CMOS static RAMs to reduce testing costs

Author

Yokoyama, Hiroshi ; Tamamoto, Hideo ; Narita, Yuichi

Author_Institution

Dept. of Inf. Eng., Akita Univ., Japan

fYear

1993

fDate

16-18 Nov 1993

Firstpage

231

Lastpage

236

Abstract

This paper presents a methodology to reduce the testing costs of a CMOS static RAMs (SRAMs), based on a current testing. In this test method, the structure of SRAMs is modified so that all the cells can be driven simultaneously. A fault in the memory cell array can be detected by only observing the abnormal current. Since the whole cell array could be treated as if it were a single cell, the length of the test sequences is not dependent on the size of the memory cell array and must be very short

Keywords

CMOS memory circuits; SPICE; SRAM chips; economics; electric current measurement; fault location; integrated circuit manufacture; integrated circuit testing; logic arrays; logic testing; CMOS; IDDQ testing; PSPICE; SPICE3; SRAMs; current testing; fault detection; fault mapping; memory cell array; static RAMs; stuck-on faults; stuck-open faults; testing costs; Circuit faults; Circuit testing; Costs; Electrical fault detection; Fault detection; Logic testing; Random access memory; Read-write memory; Semiconductor device modeling; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium, 1993., Proceedings of the Second Asian

Conference_Location

Beijing

Print_ISBN

0-8186-3930-X

Type

conf

DOI

10.1109/ATS.1993.398810

Filename

398810