Statistical retention modeling in floating-gate cell: ONO scaling

Author

Serov, Andrey ; Shin, Dongwan ; Kim, Dae Sin ; Kim, Taikyung ; Lee, Keun-Ho ; Park, Young-Kwan ; Yoo, Moon-Hyun ; Kim, Taehun ; Sung, Sug-Kang ; Lee, Choong-Ho

Author_Institution

CAE Team, Samsung Electron., Hwasung, South Korea

fYear

2009

fDate

26-30 April 2009

Firstpage

887

Lastpage

890

Abstract

The simulation study of the ONO gate stack scaling, which includes the Monte-Carlo statistical analysis of time-dependent Vth distribution and SILC is performed. Leakage through both tunneling and blocking oxide is taken into account including multi-trap tunneling paths. Exact 50 nm floating-gate cell structure is used instead of simple 1D stack for modeling and comparison with experimental data. Analysis of the influence of trap parameters on scaling trends is given.

Keywords

Monte Carlo methods; flash memories; leakage currents; statistical analysis; tunnelling; Monte-Carlo statistical analysis; ONO gate stack scaling; SILC; flash memories; floating-gate cell structure; leakage current; multitrap tunneling paths; nonvolatile memory cell scaling; size 50 nm; statistical retention modeling; time-dependent Vth distribution; Analytical models; Computer aided engineering; Dielectrics; Electron traps; Leakage current; Nonvolatile memory; Silicon compounds; Statistical analysis; Tail; Tunneling; Flash memories; dielectrics; retention modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium, 2009 IEEE International

Conference_Location

Montreal, QC

ISSN

1541-7026

Print_ISBN

978-1-4244-2888-5

Electronic_ISBN

1541-7026

Type

conf

DOI

10.1109/IRPS.2009.5173372

Filename

5173372