• DocumentCode
    2672245
  • Title

    State encoding and functional decomposition for self-checking sequential circuit design

  • Author

    Pagey, Sandeep ; Sherlekar, S.D. ; Venkatesh, G.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Bombay, India
  • fYear
    1993
  • fDate
    16-18 Nov 1993
  • Firstpage
    293
  • Lastpage
    297
  • Abstract
    In a previous paper, we presented a functional decomposition technique for low cost self-checking realizations of combinational circuits. This technique can be applied directly to the design of the next state logic of FSMs. In this paper, we present a methodology for good state encoding which results in a low cost self-checking realization of the FSM. The state encoding problem for self-checking realizations of FSMs consists of (a) the choice of a code space for state encoding, and (b) the assignment of codewords to individual states. While (b) can be solved using existing state assignment tools, (a) is addressed for the first time in this paper
  • Keywords
    design for testability; encoding; finite state machines; logic design; logic testing; sequential circuits; assignment of codewords; code space; cost; finite state machine; functional decomposition; good state encoding; self-checking sequential circuit design; Circuit faults; Computer science; Cost function; Delay; Encoding; Hardware; Logic circuits; Logic design; Paper technology; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium, 1993., Proceedings of the Second Asian
  • Conference_Location
    Beijing
  • Print_ISBN
    0-8186-3930-X
  • Type

    conf

  • DOI
    10.1109/ATS.1993.398820
  • Filename
    398820