Title :
A design of HDB3 CODEC based on FPGA
Author :
Chang-Sen, Zhang ; Qi, Xu
Author_Institution :
Coll. of Comput. Sci. & Technol., Henan Polytech. Univ., Jiaozuo, China
Abstract :
The basic principles and structure of HDB3 was briefly introduced in this paper, and the shortcomings of the existing HDB3 encoder and decoder was analyzed. Then a new design of HDB3 encoder and decoder based on FPGA was proposed, and the hardware design circuit and software simulation were introduced. The simulation was achieved through the VERILOG-HDL in EP2C35F672C8 chip of CycloneII series in the development environment of Quartus II 7.2. The results show that the design meets the requirements of HDB3 encoder and decoder, which has a simple hardware circuit and flexible software, and runs fast,and can be used in practical communication systems.
Keywords :
codecs; field programmable gate arrays; hardware description languages; logic design; CycloneII series; EP2C35F672C8 chip; FPGA; HDB3 codec design; HDB3 encoder; High Density Bipolar Codes; Quartus II 7.2; VERILOG-HDL; hardware design circuit; software simulation; Circuit simulation; Codecs; Computer science; Decoding; Digital communication; Educational institutions; Encoding; Field programmable gate arrays; Hardware; Optical fiber communication; Encoder and Decoder; FPGA; HDB3;
Conference_Titel :
Advanced Computer Control (ICACC), 2010 2nd International Conference on
Conference_Location :
Shenyang
Print_ISBN :
978-1-4244-5845-5
DOI :
10.1109/ICACC.2010.5486745
