Layout dependency of PMOS off current degradation due to off-state stress

this paper, we used 56 nm DRAM design-rule technology with dual poly gate process. PMOS in inverter had an electrical oxide thickness (t_ox) of 60 A and an effective channel length (L_eff) of 0.16 um with utilizing STI features and finger type gate structures(x2, x400). HC stress on inverter was performed at 4.3V bias(VDD) during lOksec (1MHz). Under such condition, the gate current is not dominated by Fowler-Nordheim tunneling current. PMOS in Inverter was stressed at on state (CHE,Vin=0V), dynamic state (I_gmax, I_bmax) and off-state bias (Vin=Vdd) conditions. The change in the transistor drive current (Id) was measured at the saturation condition (Vd=Zero) and the off- state leakage current (I_off) was also measured at high (PMOS) gate bias. To evaluate acceleration model and parameter, constant voltage off state stresses were conducted over a wide rage of voltage (4.3-5.8V, 0.3V step) and 3 corner temperature (35´c, 85´c, 125´c).