Title :
Use of AuSn solder bumps in three-dimensional passive aligned packaging of LD/PD arrays on Si optical benches
Author :
Itoh, Masataka ; Sasaki, Junichi ; Uda, Akihiro ; Yoneda, Isao ; Honmou, Hiroshi ; Fukushima, Kiyoshi
Author_Institution :
Opto-Electron. Res. Labs., NEC Corp, Kanagawa, Japan
Abstract :
Precise three-dimensional passive alignment of LD/PD arrays on Si optical benches has been achieved by means of AuSn solder bumps. A punch-and-die technique is used to fabricate the AuSn solder bumps to an extremely high accuracy (±2 μm) in bump height. A stripe-type bump bonding technique is employed to attain precise vertical alignment (±1 μm) of an LD array chip. Average LD-single-mode fiber array coupling loss was as low as -9.5±0.5 dB, and while that of a PD-multimode fiber array was -0.4±0.3 dB, almost as good as that with active alignment
Keywords :
gold alloys; microassembling; modules; photodiodes; semiconductor device packaging; semiconductor laser arrays; soldering; tin alloys; -0.4 dB; -9.5 dB; 3D passive aligned packaging; AuSn; AuSn solder bumps; LD array chip; LD/PD arrays; Si; Si optical benches; laser diode arrays; photodiode arrays; planar mounting technique; precise vertical alignment; punch/die technique; stripe-type bump bonding technique; Bonding; Diodes; Electronics packaging; High speed optical techniques; National electric code; Optical arrays; Optical coupling; Optical fibers; Semiconductor laser arrays; Ultraviolet sources;
Conference_Titel :
Electronic Components and Technology Conference, 1996. Proceedings., 46th
Conference_Location :
Orlando, FL
Print_ISBN :
0-7803-3286-5
DOI :
10.1109/ECTC.1996.517367
