An implementation method of a turbo-code decoder using a block-wise MAP algorithm

The several implementation methods of the MAP decoder are proposed. By using the novel time-shared process of a pipe-lined structure, the restriction of recursion process on the state metric can be efficiently conquered, and the complexity of the MAP decoder can be reduced to the order of a SOYA (soft output Viterbi algorithm) decoder. An efficient structure for the controller is also proposed for the cdma-2000 system. The designed MAP decoder using a block-wire MAP algorithm has been implemented in only one 20,000 gate circuit. It has been validated by VHDL, which has been compared with the results of the initial simulation (C programs). The designed decoder has A 300 kbps decoding processing ability with 8 times iterations on a FPGA circuit, and just has a deviation of about 01-0.2 dB over the ideal MAP decoder; even if all hardware environments were considered