Architectural topologies for NoC datapath polymorphic processors

Author

Weber, Joshua ; Oruklu, Erdal ; Saniie, Jafar

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA

fYear

2011

fDate

15-17 May 2011

Firstpage

1

Lastpage

6

Abstract

Polymorphic processors attempt to merge the benefits of general purpose processors with performance gains from reconfigurable elements. In this paper, we present a novel polymorphic processor architecture. The integration of a network-on-a-chip (NoC) architecture as a replacement for the processor datapath creates unique requirements for the NoC design. We explore multiple NoC topologies as potential candidates for the creation of a polymorphic processor. A simulator based around the network simulator 2 (ns-2) software platform is created. Standard embedded processor benchmark programs are simulated to explore critical parameters and NoC design decisions impacting the performance of the polymorphic processor.

Keywords

general purpose computers; hardware-software codesign; network topology; network-on-chip; reconfigurable architectures; NoC datapath; NoC design; NoC topologies; architectural topologies; embedded processor; general purpose processors; network simulator 2 software; network-on-a-chip architecture; polymorphic processor architecture; polymorphic processors; reconfigurable elements; Benchmark testing; Clocks; Computer architecture; Delay; Network topology; Program processors; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electro/Information Technology (EIT), 2011 IEEE International Conference on

Conference_Location

Mankato, MN

ISSN

2154-0357

Print_ISBN

978-1-61284-465-7

Type

conf

DOI

10.1109/EIT.2011.5978621

Filename

5978621