Optimizing the performance of turbo code HDL model for rapid prototype

Turbo code is a class of convolutional codes which have great deal of interest as they attain the ultimate limits of the capacity of communication channel. They are known as ¿The ultimate Error Control Codes¿ which made them move rapidly from research laboratories to practical applications throughout the world. The use of these codes has been proposed for several applications where highly reliable transmission is required at very low SNR. In this paper we discuss hardware implementation aspect of turbo codes along with some previous work done and their limitations. We also present the results of RTL modeling and simulation and the synthesis report of turbo encoder using Xilinx ISE 10.1. The performance of turbo codes can be optimized in terms of power consumption and resource utilization of hardware.