DocumentCode :
2674725
Title :
Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
fYear :
2000
fDate :
25-27 Oct. 2000
Abstract :
The following topics were dealt with. Yield analysis/modelling; yield enhancement; wafer scale/large-area systems; fault-tolerant interconnections; fault-tolerant systems; error coding; reconfiguration and repair; online testing; BIST; testing strategies; IDDQ testing; and fault injection.
Keywords :
VLSI; built-in self test; fault tolerant computing; integrated circuit interconnections; integrated circuit testing; integrated circuit yield; reconfigurable architectures; wafer-scale integration; BIST; I/sub DDQ/ testing; error coding; fault injection; fault-tolerant interconnections; fault-tolerant systems; large-area systems; online testing; reconfiguration; repair; testing strategies; wafer scale systems; yield analysis; yield enhancement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
Conference_Location :
Yamanashi, Japan
ISSN :
1550-5774
Print_ISBN :
0-7695-0719-0
Type :
conf
DOI :
10.1109/DFTVS.2000.886967
Filename :
886967
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2674725
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