Title :
IC critical volume calculation through ray-casting of CSG trees
Author :
Moran, Mike ; Allan, Gerard A.
Author_Institution :
Dept. of Electron. & Electr. Eng., Edinburgh Univ., UK
Abstract :
This paper describes a method of finding the critical volume of integrated circuit (IC) layers. The aim of the technique is to calculate metrics of an IC that can be used to estimate the chip yield. The layout itself and the defects that arise in production are considered to be three-dimensional, as opposed to two-dimensional, objects
Keywords :
computational geometry; integrated circuit layout; integrated circuit yield; trees (mathematics); 3D objects; CSG trees; IC critical volume calculation; IC metrics calculation; chip yield estimation; constructive solid geometry trees; defects; integrated circuit layers; ray-casting; three-dimensional objects; Application specific integrated circuits; Costs; Geometry; Integrated circuit layout; Integrated circuit yield; Production; Shape; Solids; Three-dimensional integrated circuits; Yield estimation;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
Conference_Location :
Yamanashi
Print_ISBN :
0-7695-0719-0
DOI :
10.1109/DFTVS.2000.886969
