• DocumentCode
    2674871
  • Title

    Trends in megabit DRAM circuit design

  • Author

    Itoh, Kiyoo

  • Author_Institution
    Hitachi Ltd., Tokyo, Japan
  • fYear
    1989
  • fDate
    17-19 May 1989
  • Firstpage
    21
  • Lastpage
    27
  • Abstract
    The state of the art in megabit dynamic RAM (DRAM) circuit and chip design is reviewed in terms of essential design parameters such as signal-to-noise ratio (S/N), power dissipation, speed and power supply standardization. On the basis of this discussion, some possibilities for capacities greater than 16 Mb are presented, stressing the role of BiCMOS technology. It is shown how S/N ratio, power dissipation and speed are closely related to continued DRAM progress. From the DRAM trends, it is predicted that the current DRAM technology might be diversified to both large-memory-capacity-oriented technology and to high-speed-oriented technology, posing power supply standardization as a continuing serious concern
  • Keywords
    BIMOS integrated circuits; integrated memory circuits; random-access storage; BiCMOS technology; S/N ratio; chip design; circuit design; design parameters; dynamic RAM; high-speed-oriented technology; large-memory-capacity-oriented technology; megabit DRAM; power dissipation; power supply standardization; speed; BiCMOS integrated circuits; Chip scale packaging; Circuit synthesis; DRAM chips; Power dissipation; Power supplies; Random access memory; Signal design; Signal to noise ratio; Standardization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
  • Conference_Location
    Taipei
  • Type

    conf

  • DOI
    10.1109/VTSA.1989.68574
  • Filename
    68574