Title :
Low complexity encoding of improved regular LDPC codes
Author :
Chae, Su-Chang ; Park, Yun-Ok
Author_Institution :
Mobile Telecomm. Lab., Electron. Telecomm. Res. Institutes, Daejeon, South Korea
Abstract :
The existing encoding scheme for LDPC codes usually incurs too high complexity and should be changed to a low complexity encoding scheme. However, little consideration has been given to the LDPC encoder VLSI implementation. We consider low complexity encoding of regular LDPC codes, and we propose a pivoting and bit-reverse (PABR) algorithm to rapidly construct the parity-check matrix (PCM). And we consider improved regular LDPC codes in BER performance. We propose that the PCM is constructed with sub-matrixes which are made up of Costas arrays. The codes have sparse PCMs. They are designed to perform well when iteratively decoded with the sum-product decoding algorithm and to allow low complexity encoding. We show an approach to implementing the LDPC encoder using the PABR algorithm and improving BER performance using a PCM with Costas arrays. This paper then describes an FPGA implementation of regular LDPC encoder on a hardware platform for 4G mobile communication systems.
Keywords :
4G mobile communication; VLSI; channel coding; error statistics; field programmable gate arrays; iterative decoding; parity check codes; sparse matrices; 4G mobile communication system; BER; Costas array sub-matrices; FPGA implementation; LDPC encoder; PABR algorithm; VLSI implementation; channel coding; iterative decoding; low complexity encoding; pivoting/bit-reverse algorithm; regular LDPC codes; sparse parity-check matrix; sum-product decoding; Algorithm design and analysis; Bit error rate; Encoding; Field programmable gate arrays; Iterative algorithms; Iterative decoding; Parity check codes; Phase change materials; Sparse matrices; Very large scale integration;
Conference_Titel :
Vehicular Technology Conference, 2004. VTC2004-Fall. 2004 IEEE 60th
Print_ISBN :
0-7803-8521-7
DOI :
10.1109/VETECF.2004.1400513