A VLSI algorithm for a systolic array implementation of type IV DST based on a pseudo-band correlation structure

A new design approach to derive a systolic array architecture for a prime length type IV discrete sine transform based on a regular and modular computational structure is presented. This approach is based on a VLSI algorithm that uses an appropriate restructuring method of type IV DST into a regular computational structure. It uses a new computational structure that was called band-correlation as basic computational form that is appropriate for a VLSI implementation. The proposed algorithm can be mapped onto a linear systolic array that have a small number of I/O channels and low I/O bandwidth and can be efficiently implemented into a VLSI chip. An efficient VLSI chip can be thus obtained that have good architectural topology, processing speed, hardware complexity, I/O costs and throughput.