Differential based area efficient ROM-less Quadrature Direct Digital Frequency Synthesis

Quadrature direct digital frequency synthesis (QDDFS) is a technique which can generate sine and cosine values in digital domain. In this paper we present a novel architecture for implementing QDDFS, suitable for implementation in very large scale integration (VLSI). The algorithm is very simple, which leads to a reduced hardware complexity. It takes two seed values and depending upon the input frequency control word, the algorithm is capable of generating different frequencies. Hardware is ROM-less, making the proposed scheme more area efficient than ROM based lookup table algorithms. In terms of speed performance, the architecture proposed in this paper is more time efficient than coordinate rotation digital computer (CORDIC) based QDDFS and Singleton´s method. Simulation results show that the generated values are very close to the actual values.