Title :
A 58 ns 4 Mb CMOS DRAM with an effective one-shot gate address buffer
Author :
Miyamoto, Hiroshi ; Yamagata, Tadato ; Mori, Shigeru ; Ogoh, Ikuo ; Nagatomo, Masao ; Yamada, Michihiro
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
A 4-Mb CMOS dynamic RAM (DRAM) with an effective one-shot gate address buffer has been fabricated. The buffer greatly reduces row address hold time, which gives a fast RAS (row-address strobe) access time of 58 ns. The RAM also implements a novel standby current limitation circuit, which saves the current in the first stage of the buffer even with the TTL-level input voltage. The memory cell has a stacked capacitor. The RAM measures 6.84 mm×14.95 mm and is housed in a 350-mil small-outline J-leaded (SOJ) package and a 400-mil zig-zag in-line package (ZIP)
Keywords :
CMOS integrated circuits; buffer storage; integrated memory circuits; limiters; random-access storage; 4 Mbit; 58 ns; CMOS DRAM; SOJ; ZIP; dynamic RAM; memory cell; one-shot gate address buffer; row address hold time; small outline J-leaded package; stacked capacitor; standby current limitation circuit; zig-zag in-line package; Clocks; Content addressable storage; Large scale integration; Power dissipation; Pulse generation; Random access memory; Read-write memory; Research and development; Timing; Voltage;
Conference_Titel :
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location :
Taipei
DOI :
10.1109/VTSA.1989.68575
