Title :
A high efficiency and high linearity power amplifier utilizing post-linearization technique for 5.8 GHz DSRC applications
Author :
Liu, Qing ; Jiangtao, Sun ; Shu, YongJu ; Horie, Koji ; Itoh, Nobuyuki ; Yoshimasu, Toshihiko
Author_Institution :
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan
Abstract :
In this paper, a post-linearization technique of cascode CMOS power amplifier is presented. The proposed method adopts two cascode FET, one operates in class AB mode and the other works near class B mode, which absorbs the nonlinear current of third-order intermodulation distortion (IMD). The proposed method is investigated for 5.8 GHz Dedicated Short Range Communication (DSRC) applications, and fabricated by 0.13 μm CMOS process. The measured results show that the proposed power amplifier exhibited a power gain of 11.5 dB, an output power of 1 dB compression point (P1dB) of 17.3 dBm, a power added efficiency (PAE) of 32% at P1dB with a low voltage operation of 2.0 V. The improvement in IMD of 6 dB over large output power range and a maximum improvement of 12 dB were achieved.
Keywords :
CMOS integrated circuits; power amplifiers; CMOS process; DSRC application; cascode CMOS power amplifier; dedicated short range communication; frequency 5.8 GHz; high linearity power amplifier; post-linearization technique; power added efficiency; power gain; third-order intermodulation distortion; CMOS integrated circuits; CMOS technology; Capacitance; Gain; Linearity; Logic gates; Power amplifiers; CMOS power amplifier; DSRC; IMD; post-linearization technique;
Conference_Titel :
Power Amplifiers for Wireless and Radio Applications (PAWR), 2011 IEEE Topical Conference on
Conference_Location :
Phoenix, AZ
Print_ISBN :
978-1-4244-8416-4
Electronic_ISBN :
978-1-4244-8415-7
DOI :
10.1109/PAWR.2011.5725375
