Superior Improvements in GIDL and Retention by Fluorine Implantation in Saddle-Fin Array Devices for Sub-40-nm DRAM Technology

Author

Chia-Ming Yang ; Jer-Chyi Wang ; Wei-Ping Lee ; Chien-Chi Lee ; Chih-Hung Lin ; Chung Yuan Lee ; Jo-Hui Lin ; Hsin-Huei Chen ; Chih-Yuan Hsiao ; Ruey-Dar Chang ; Chao-Sung Lai

Author_Institution

Dept. of Electron. Eng., Chang Gung Univ., Taoyuan, Taiwan

Volume

34

Issue

9

fYear

2013

fDate

Sept. 2013

Firstpage

1124

Lastpage

1126

Abstract

A highly improved method to reduce gate-induced drain leakage and retention fail bit counts is proposed for use in the sub-40-nm dynamic random access memory technologies. Fluorine (F) implantation with different dose post-gate oxidation is used for investigating the performance of saddle-fin (S-Fin) array devices. Significantly lower retention fail counts of 35% are achieved in the S-Fin device using a medium dosage of F implantation. Random telegraph signal-like fluctuation can also be improved using the proposed F implantation method. Trap passivation by F atoms in the source and the drain areas could have led to the improvements seen in the experiments.

Keywords

DRAM chips; fluorine; ion implantation; oxidation; DRAM technology; GIDL; dose post-gate oxidation; dynamic random access memory; fluorine implantation; gate-induced drain leakage; random telegraph signal-like fluctuation; saddle-fin array device; trap passivation; Doping; Logic gates; Passivation; Performance evaluation; Random access memory; Silicon; Transistors; Dynamic random access memory (DRAM); fluorine (F) implantation; gate-induced drain leakage (GIDL); retention;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2013.2271274

Filename

6553604