A reconfigurable WSI massively data-parallel processing device for cost-effective 3D sensor data processing

Author

Lea, R.M. ; Tetnowski, P.T. ; Covic, M.

Author_Institution

Brunel Univ., Uxbridge, UK

fYear

2000

fDate

2000

Firstpage

87

Lastpage

95

Abstract

A performance-scalable ISDP (Interactive Sensor Data Processing) workstation, accelerated with commercial PCI multiprocessor cards, is described and a WSI massively data-parallel processor (MdPP) device is proposed for the replacement of its VLSI processors. Delivering 60 GOPS for 16-bit integer multiply-accumulate operations, a WSI-FPGA implementation of the reconfigurable device is shown to be better suited to ISDP applications and at least two orders-of-magnitude more cost-effective

Keywords

add-on boards; field programmable gate arrays; parallel processing; pipeline processing; reconfigurable architectures; sensor fusion; wafer-scale integration; 16 bit; FPGA implementation; Interactive Sensor Data Processing; PCI multiprocessor cards; cost-effective 3D sensor data processing; massively data-parallel processing device; multiply-accumulate operations; performance-scalable ISDP; reconfigurable WSI; Acceleration; Bandwidth; Data processing; Engines; Multimedia systems; Parallel processing; Pipelines; Sensor phenomena and characterization; Sensor systems; Ultrasonic imaging;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on

Conference_Location

Yamanashi

ISSN

1550-5774

Print_ISBN

0-7695-0719-0

Type

conf

DOI

10.1109/DFTVS.2000.887146

Filename

887146