Title :
Design of switching blocks tolerating defects/faults in FPGA interconnection resources
Author :
Doumar, Abderrahim ; Ito, Hideo
Author_Institution :
Graduate Sch. of Sci. & Technol., Chiba Univ., Japan
Abstract :
Field programmable gate array is mainly composed of the interconnection resources area. Related defects/faults are therefore more probable than defects/faults in other regions of the chip. In this paper we propose a new approach tolerating defects/faults in interconnection resources. This approach is based on the modification of the switching block structure so that defects/faults could be avoided. Defects/faults are avoided with only an average of 3% delay overhead and partial modification of the original data. The yield is significantly improved comparing with actual chips. The area overhead is required in this approach. However, it is proved that it is reasonable comparing with other approaches
Keywords :
fault tolerant computing; field programmable gate arrays; integrated circuit interconnections; integrated circuit yield; logic design; 3% delay overhead; FPGA interconnection; area overhead; delays; field programmable gate array; interconnection resources; modification; partial modification; switching blocks; yield; Circuit faults; Costs; Delay; Fault tolerance; Field programmable gate arrays; Integrated circuit interconnections; Production; Programmable logic arrays; Sequential circuits; Switches;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
Conference_Location :
Yamanashi
Print_ISBN :
0-7695-0719-0
DOI :
10.1109/DFTVS.2000.887151
