Title :
Fault-tolerant high-performance CORDIC processors
Author :
Kwa, Jae-Hyuck ; Piuri, Vincenzo ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
This paper presents a low-cost approach to concurrent error detection in a high-performance CORDIC processor based on a conditional-sum scheme. The specific characteristics of the CORDIC computation and the processor allow fault detection at a low increase in circuit complexity and latency. The detection scheme is based on use of the AN codes for the arithmetic part and on duplication of the rotation direction generators. Granular-pipelining has been applied to provide a variety of different performance tradeoffs, all with the same fault detection capabilities
Keywords :
VLSI; circuit complexity; digital arithmetic; digital signal processing chips; error detection; iterative methods; parallel architectures; pipeline arithmetic; AN codes; CORDIC processors; circuit complexity; concurrent error detection; conditional-sum; duplication; fault detection; granular-pipelining; iterative techniques; latency; rotation direction generators; Arithmetic; Complexity theory; Computer errors; Delay; Electrical fault detection; Fault tolerance; Hardware; Pipeline processing; Redundancy; Throughput;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
Conference_Location :
Yamanashi
Print_ISBN :
0-7695-0719-0
DOI :
10.1109/DFTVS.2000.887154
