A fault-tolerant 176 Gbit solid state mass memory architecture

Author

Cardarilli, G.C. ; Marinucci, P. ; Ottavi, M. ; Salsano, A.

Author_Institution

Dept. of Electron. Eng., Rome Univ., Italy

fYear

2000

fDate

2000

Firstpage

173

Lastpage

180

Abstract

This paper presents a new Solid State Mass Memory (SSMM) suitable for space applications. The memory reliability is increased by using two different approaches. Firstly, memory mass fault-tolerance, with respect to hard failures, is obtained by using a fine-granularity hierarchical structure with a certain level of redundancy. A second strategy used for facing soft errors is based on Error Correction Codes (ECC) and periodic memory washing. A performance index has been developed for evaluating the main parameters of the SSMM architecture. This index takes into account the ECC capability, the memory weight and reliability, allowing to relate them to the required overhead

Keywords

error correction codes; fault tolerant computing; memory architecture; modules; performance index; redundancy; storage management chips; 176 Gbit; 176 Gbit solid state mass memory architecture; Error Correction Codes; SSMM architecture; crossbar switch matrix; fine-granularity hierarchical structure; hard failures; memory mass fault-tolerance; memory modules; memory reliability; memory weight; overhead; performance index; periodic memory washing; redundancy; serial link interface; soft errors; space applications; unidirectional interface; Data security; Error correction codes; Face detection; Fault tolerance; Instruments; Memory architecture; Performance analysis; Redundancy; Samarium; Solid state circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on

Conference_Location

Yamanashi

ISSN

1550-5774

Print_ISBN

0-7695-0719-0

Type

conf

DOI

10.1109/DFTVS.2000.887155

Filename

887155