Design for testability to achieve high test coverage. A case study

Author

Mukherjee, Sukalyan

fYear

2000

fDate

2000

Firstpage

320

Lastpage

328

Abstract

With the advent of the System-On-a-Chip (SoC) and mass production of these complex ICs, the design of an ASIC with testability features in it has become a mandatory requirement. Testability requirements are present in various levels of an SoC. The internal gates of the chip should be made testable for stuck-at faults. Internal hard-macros need to be tested for manufacturing defects. The connection of the pads with the external pins are to be tested for bonding faults. Chips placed on boards are to be tested for the pin connection integrity on the board. Different methods are used to test each of these defects. This paper discusses various design/implementation issues typically need to be considered for designing a circuitry for testability, achieving high test coverage in less test time. EnThink Inc.´s (a WIPRO Company) synthesizable core for OHCI (Open Host Controller Interface) over IEEE 1394 Link layer implementation is used as a reference in this paper

Keywords

VLSI; application specific integrated circuits; design for testability; integrated circuit design; integrated circuit testing; logic testing; ASIC DFT; ASIC testability features; EnThink synthesizable core; OHCI; SoC testability; bonding faults; design for testability; high test coverage; internal hard-macros; manufacturing defects; open host controller interface; pin connection integrity; stuck-at faults; system-on-a-chip; Application specific integrated circuits; Bonding; Circuit faults; Circuit testing; Design for testability; Manufacturing; Mass production; Pins; System testing; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on

Conference_Location

Yamanashi

ISSN

1550-5774

Print_ISBN

0-7695-0719-0

Type

conf

DOI

10.1109/DFTVS.2000.887172

Filename

887172