Title :
Path delay fault testability analysis
Author :
Sosnowski, Janusz ; Wabia, Tomasz ; Bech, Tomasz
Author_Institution :
Inst. of Comput. Sci., Warsaw Univ. of Technol., Poland
Abstract :
The paper deals with the problem of testing delay path faults. We present results obtained with a newly developed test pattern generator. This generator is based on the use of reduced ordered binary decision diagrams (ROBDDs) and reveals many advantages as compared with other ATPGs published in the literature. An important contribution of the paper is the analysis of various testability features of digital circuits in respect to path delay faults. It was applied to the ISCAS89 benchmark and other circuits. The proposed testability measures are helpful in codesigning deterministic and pseudorandom delay tests as well as in improving circuit testability
Keywords :
VLSI; automatic test pattern generation; binary decision diagrams; delays; digital integrated circuits; integrated circuit testing; logic testing; ATPG module; ROBDD; VLSI circuits; binary decision diagrams; circuit testability improvement; deterministic delay tests; digital circuits; path delay fault testability analysis; pseudorandom delay tests; reduced ordered BDD; test pattern generator; testability measures; Automatic test pattern generation; Benchmark testing; Boolean functions; Circuit faults; Circuit testing; Data structures; Delay effects; Robustness; Test pattern generators; Timing;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
Conference_Location :
Yamanashi
Print_ISBN :
0-7695-0719-0
DOI :
10.1109/DFTVS.2000.887174
