DocumentCode
2676737
Title
Testability analysis of IDDQ testing with large threshold value
Author
Hashizume, Masaki ; Yotsuyanagi, Hiroyuki ; Tamesada, Takeomi ; Takeda, Masashi
Author_Institution
Fac. of Eng., Tokushima Univ., Japan
fYear
2000
fDate
2000
Firstpage
367
Lastpage
375
Abstract
By using large threshold value in IDDQ tests, test time can be shortened. However, the fault coverage of the IDDQ tests will be affected by process variation. In this paper, effects on fault coverage of IDDQ tests generated by variations of zero biased threshold voltage of each MOS transistor in a circuit under test are examined with a circuit simulator. The result suggests us that IDDQ testing with large threshold value is applicable to production tests of CMOS ICs
Keywords
CMOS logic circuits; integrated circuit testing; leakage currents; logic testing; production testing; CMOS ICs; IDDQ testing; MOS transistor; circuit simulator; fault coverage; large threshold value; process variation; production tests; test time reduction; testability analysis; zero biased threshold voltage variations; CMOS logic circuits; Capacitance; Circuit faults; Circuit testing; Current measurement; Current supplies; Fluid flow measurement; Integrated circuit testing; Logic testing; Production;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
Conference_Location
Yamanashi
ISSN
1550-5774
Print_ISBN
0-7695-0719-0
Type
conf
DOI
10.1109/DFTVS.2000.887177
Filename
887177
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