Title :
Fault injection in VHDL descriptions and emulation
Author_Institution :
TIMA Lab., Inst. Nat. Polytech. de Grenoble, Grenoble, France
Abstract :
Analyzing at an early stage of the design the potential faulty behaviors of a circuit becomes a major concern due to the increasing probability of faults. It is proposed to carry out such an analysis using fault injections in RT-level VHDL descriptions and hardware prototyping of the circuit under design. Injection of erroneous transitions is automated and results are presented
Keywords :
fault tolerant computing; field programmable gate arrays; hardware description languages; high level synthesis; probability; RT-level VHDL descriptions; VHDL descriptions; erroneous transitions; fault injection; hardware prototyping; potential faulty behaviors; probability; Circuit faults; Costs; Electrical fault detection; Emulation; Failure analysis; Hardware; Integrated circuit technology; Laboratories; Performance analysis; Prototypes;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
Conference_Location :
Yamanashi
Print_ISBN :
0-7695-0719-0
DOI :
10.1109/DFTVS.2000.887182
