The design of a RSSI for the GPS receiver

This paper describes CMOS circuit design techniques for a limiting amplifier and received signal strength indicator (RSSI) circuits for the GPS receiver. The circuits in limiting amplifier and RSSI are all preudo differential to minimize the requirement of the supply voltage and be prepared against device mismatch. A folded diode load and folded cascade structure gain cell is introduced for each gain cell of the amplifier. The architecture of the offset subtractor is a cross-connected source-coupled pair. Based on SMIC 0.18 μm CMOS Technology with a 1.8 V supply, the RSSI provides 55 dB of log-linear range with less than 1.5 dB error due to process variation. The overall power consumption is 3.7 mW.