مرکز منطقه ای اطلاع رساني علوم و فناوري - Efficient Technique to Reduce Gate Evaluations and Speed up Fault Simulation

DocumentCode :

2676968

Title :

Efficient Technique to Reduce Gate Evaluations and Speed up Fault Simulation

Author :

Kumar, P. R Suresh ; Srinivas, M.K. ; Jacob, James

Author_Institution :

HAL, Bangalore

fYear :

1993

fDate :

3-6 Jan 1993

Firstpage :

104

Lastpage :

104

Keywords :

Central Processing Unit; Circuit faults; Circuit simulation; Circuit testing; Discrete event simulation; Electrical fault detection; Fault detection; Jacobian matrices; Logic circuits; Sun;

fLanguage :

English

Publisher :

ieee

Conference_Titel :

VLSI Design, 1993. Proceedings. The Sixth International Conference on

ISSN :

1063-9667

Print_ISBN :

0-8186-3180-5

Type :

conf

DOI :

10.1109/ICVD.1993.669650

Filename :

669650

Link To Document :

https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2676968