DocumentCode
267732
Title
Impact analysis of resistive bridge within deep submicron Secured CMOS circuits
Author
Ait Abdelmalek, G. ; Ziani, R.
Author_Institution
Dept. of Electron., Mouloud Mammeri Univ., Tizi-ouzou, Algeria
fYear
2014
fDate
16-18 Dec. 2014
Firstpage
112
Lastpage
117
Abstract
This article takes a first step in the field of secured circuits testing and characterization of associated fault models. We analyze the electrical impact of the resistive bridge defect in deep-submicron secured circuits, implemented in WDDL and in SecLib. The quality of this analysis is verified by SPICE simulations. It is shown that the detection of defect depends on the bridging resistance value. It is also shown, that the WDDL is more vulnerable than SecLib.
Keywords
CMOS logic circuits; bridge circuits; circuit simulation; fault simulation; integrated circuit reliability; integrated circuit testing; SPICE simulations; WDDL; circuit testing; deep submicron secured CMOS circuits; defect detection; electrical impact; fault models; impact analysis; resistive bridge; wave dynamic differential logic; Bridge circuits; Circuit faults; Delays; Integrated circuit modeling; Logic gates; Resistance; Semiconductor device modeling; asynchronous circuits; fault models; resistive bridging faults; small delay faults; testability;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium (IDT), 2014 9th International
Conference_Location
Algiers
Type
conf
DOI
10.1109/IDT.2014.7038597
Filename
7038597
Link To Document