A low temperature 12 ns DRAM

Author

Henkels, W.H. ; Lu, N.C.C. ; Hwang, W. ; Rajeevakumar, T.V. ; Franch, R.L. ; Jenkins, K.A. ; Bucelot, T.J. ; Heidel, D.F. ; Immediato, M.J.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1989

fDate

17-19 May 1989

Firstpage

32

Lastpage

35

Abstract

Results are presented of measurements on cryogenic operation of a high-speed 512-kb CMOS dynamic RAM (DRAM). Comprehensive investigations focused on circuit concerns particularly relevant to high speed. The measured access time was 12 ns, and the results show that noise, power, and soft error rate do not preclude very-high-speed DRAM operation at cryogenic temperatures. Compared to room-temperature operation the observed improvement in access time was about 1.7× for V _DD=5 V. Compared to 85°C operation the improvement was 2.2×

Keywords

CMOS integrated circuits; cryogenics; integrated memory circuits; random-access storage; 12 ns; 512 kbit; 77 K; CMOS dynamic RAM; DRAM; access time; cryogenic operation; high speed memory IC; low temperature; Circuit noise; Circuit testing; Copper; Cryogenics; MOS devices; Power measurement; Random access memory; Semiconductor device measurement; Temperature measurement; Temperature sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Conference_Location

Taipei

Type

conf

DOI

10.1109/VTSA.1989.68576

Filename

68576