Architecture of Configurable K-Way C-Access Interleaved Memory

A new efficient memory system approach towards realizing configurable C-access interleaved memory architecture has been described in this paper. Massively decreasing size, power consumption and cost of digital circuits mainly lead the development of memory architectures for pipelined processors, multiprocessors and VLIW processors. This evolves the development of high-throughput memory system by using interleaved memory architecture and provides flexibility by configuring interleaved factor for K-way interleaved memory architecture. It employs N = 2ⁿ identical memory modules of W-words, each word of B-byte size, which can be configured as K-way (K=1, 2, 4, ..., N i.e.; K ∈ 2^k, where 0≤k≤n) interleaved memory system and its data bus and address bus can be internally programmed/controlled by Data Routing Scheme (DRS) and Address Decoding Scheme (ADS) respectively. In the proposed system, processor configures the interleaving factor of the memory organization through the system data bus by a set of control bits of n+1.