A low cost analog FIR channel select filter for wireless receiver

This paper proposes a novel analog FIR low pass filtering scheme. Instead of using one FIR filter with large number of coefficients, three cascaded FIR filters with the smaller number of coefficients are used. This scheme is robust against to the coefficient error induced by actual fabrication processes. In addition, the reduced number of switches leads to the small chip area. These allow the small and accurate analog filter to be implemented with deep-submicron digital CMOS process. This filter has a stop band rejection of more than 40 dB, IIP3 of +12.5 dBm, while consuming 1.2 mW power from 1.2 V power supply at sampling frequency of 36 MHz. The core chip area is 0.23 mm².