Title :
Phase-frequency synthesis using PLL-networks
Author :
Iyer, S.P.A. ; Oliaei, Omid
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA
Abstract :
Conventional phase locked loop (PLL)-networks used for phase synthesis lack accurate frequency controllability. We describe a novel phase-frequency synthesizer architecture based on coupled-PLLs suitable for communication systems. We also present the phase noise analysis of the proposed architecture and demonstrate its superior phase noise performance compared with conventional coupled-PLLs.
Keywords :
frequency control; frequency synthesizers; phase locked loops; phase noise; voltage-controlled oscillators; PLL-networks; VCO; communication system; frequency controllability; phase locked loop networks; phase noise analysis; phase-frequency synthesis; Charge pumps; Computer architecture; Control system synthesis; Frequency synthesizers; Phase detection; Phase frequency detector; Phase locked loops; Phase noise; Phased arrays; Signal synthesis;
Conference_Titel :
Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4244-2331-6
Electronic_ISBN :
978-1-4244-2332-3
DOI :
10.1109/NEWCAS.2008.4606307
