A high-speed, low-power 16-bit 0.25 /spl mu/m GaAs binary look-ahead carry (BLC) adder based on NOR gates for wireless video communication

Author

Enomoto, T. ; Hirobe, A. ; Satoh, T. ; Fujii, M. ; Yoshida, N. ; Wada, S. ; Tokushima, M.

Author_Institution

Chuo Univ., Tokyo, Japan

fYear

1999

fDate

21-24 Feb. 1999

Firstpage

151

Lastpage

155

Abstract

A fast, low-power, and small 16-bit adder was fabricated using 0.25-/spl mu/m GaAs HJFET technology for future wireless video communication. This adder, which uses negative logic binary look-ahead carry (BLC) structure based on NOR gates, operates at the maximum clock frequency of 1.67 GHz and consumes 134.4 mW at a supply voltage of 0.6 V. The active area is 1.6 mm/sup 2/ and there are about 1,230 FETs.

Keywords

III-V semiconductors; JFET integrated circuits; adders; carry logic; digital arithmetic; gallium arsenide; logic gates; visual communication; 0.25 micron; 0.6 V; 1.67 GHz; 134.4 mW; 16 bit; FET; GaAs; III V semiconductor; NOR gates; active area; binary look-ahead carry adder; high-speed adder; low-power adder; maximum clock frequency; negative logic; power consumption; supply voltage; wireless video communication; Adders; Clocks; Coupling circuits; FETs; Gallium arsenide; Logic circuits; Power dissipation; Samarium; Video compression; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Technologies for Wireless Applications, 1999. Digest. 1999 IEEE MTT-S Symposium on

Conference_Location

Vancouver, BC, Canada

Print_ISBN

0-7803-5152-5

Type

conf

DOI

10.1109/MTTTWA.1999.755145

Filename

755145