A power efficient hold-friendly flip-flop

In this paper a hold-friendly scan flip-flop is introduced whose scan pin hold characteristic has improved while data pin timing and power are left intact. This characteristic helps to resolve scan chain hold problem while meeting the maximum frequency in data path. This solution can reduce the number of buffers inserted in the scan chain to fix hold violations. The new flip-flop can save up to 27% area and 15% power as compared to the usage of normal flip-flops combined with hold-fixing buffers.