Title :
Integrating wrapper design, TAM assignment, and test scheduling for SOC test optimization
Author :
Harmanani, Haidar M. ; Farah, Rana
Author_Institution :
Dept. of Comput. Sci. & Math., Lebanese American Univ., Byblos
Abstract :
Test time minimization for core-based designs is tightly integrated with wrapper design and TAM capacity. This paper presents a method to determine minimum SOC test schedules with wrapper design and TAM optimization based on simulated annealing. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results using the ITC 2002 benchmarks.
Keywords :
integrated circuit testing; scheduling; simulated annealing; system-on-chip; ITC 2002 benchmarks; SOC test optimization; TAM assignment; core-based design; simulated annealing; test scheduling; wrapper design; Benchmark testing; Computational modeling; Computer science; Design optimization; Mathematics; Minimization methods; Packaging; Processor scheduling; Simulated annealing; Wires;
Conference_Titel :
Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on
Conference_Location :
Montreal, QC
Print_ISBN :
978-1-4244-2331-6
Electronic_ISBN :
978-1-4244-2332-3
DOI :
10.1109/NEWCAS.2008.4606343
