A new residue adder with redundant binary number representation

Author

Wei, Shugang

Author_Institution

Dept. of Production Sci. & Technol., Gunma Univ., Kiryu

fYear

2008

fDate

22-25 June 2008

Firstpage

157

Lastpage

160

Abstract

In this paper, we present a modified addition algorithm modulo m with a signed-digit(SD) number representation where m = 2ⁿ-1, 2ⁿ or 2ⁿ+1. To simplify an SD full adder, new addition rules are proposed for generating the intermediate sum and carry with a binary number representation. By using the new codes for intermediate sum and carry and the end-around carry architecture, the proposed modulo m addition requires less hardware and short delay time for the residue addition than previous methods. Compared to previous work, the circuit area and delay time are improved by 21% and 30%, respectively.

Keywords

adders; carry logic; delays; redundant number systems; residue number systems; SD full adder; addition algorithm modulo; delay time; end-around carry architecture; redundant binary number representation; residue adder; signed-digit number; sum and carry architecture; Adders; Algorithm design and analysis; Arithmetic; Circuits; Delay effects; Equations; Hardware; Production;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on

Conference_Location

Montreal, QC

Print_ISBN

978-1-4244-2331-6

Electronic_ISBN

978-1-4244-2332-3

Type

conf

DOI

10.1109/NEWCAS.2008.4606345

Filename

4606345