Title :
A 15 Bit 95 dB Low Power Discrete Time Sigma Delta Modulator
Author :
Sohel, Mohammed Arifuddin ; Reddy, K. Chenna keshava ; Sattar, Syed Abdul ; Jabeen, Salma
Author_Institution :
Muffakham Jah Coll. of Eng. & Tech., Hyderabad, India
Abstract :
This paper presents a high resolution low power sigma delta modulator for analog to digital conversion (ADC) over 5 MHz band. The modulator consists of a third order design operating at a Sampling Frequency of 1 GHz, thus giving an over sampling ratio (OSR) of 100. A Discrete Time Switched Capacitor based design is implemented, which achieves a Signal to Quantization Noise Ratio (SQNR) of 95.3dB, leading to a 15 bit resolution of the ADC. A very low power consumption of 2.3mW at a supply voltage of 1.8V is achieved in 0.18micron CMOS technology. The 60 meter band or 5 MHz band is a relatively new amateur radio band that is useful for disaster management and this paper presents an ADC that can be used for this band.
Keywords :
CMOS integrated circuits; low-power electronics; quantisation (signal); sigma-delta modulation; switched capacitor networks; ADC; CMOS technology; OSR; SQNR; amateur radio band; analog to digital conversion; disaster management; discrete time switched capacitor based design; frequency 1 GHz; frequency 5 MHz; high resolution low power sigma delta modulator; low power discrete time sigma delta modulator; noise figure 95.3 dB; over sampling ratio; power 2.3 mW; power consumption; signal to quantization noise ratio; size 0.18 mum; storage capacity 15 bit; voltage 1.8 V; CMOS integrated circuits; Capacitors; Frequency modulation; Sigma delta modulation; Switches; Transistors; Discrete Time; High Resolution ADC; Low Pass; Low Power; Noise Shaping; Oversampling; Sigma Delta Modulation; Switched Capacitor;
Conference_Titel :
Computing Sciences (ICCS), 2012 International Conference on
Conference_Location :
Phagwara
Print_ISBN :
978-1-4673-2647-6
DOI :
10.1109/ICCS.2012.1