Wafer scale integration (WSI) of programmable gate arrays (PGA´s)

Wafer scale integration of memories by row and column repair follows a well established path developed in industry for the repair of large DRAM´s. Rows and columns in these memories can be diagnosed and those found faulty can be replaced by spares. If the entire wafer of dies can be fully repaired then all the cells on the wafer may be interconnected using artwork for chip to chip wiring which is the same on all wafers. What one would like is a similar approach which could be applied to logic circuits. Traditionally, however, logic is viewed as being inherently less regular than memory. This paper addresses one approach to accomplishing WSI based on a highly regular, restructurable logic component known as Programmable Gate Array (PGA), which is also known as a Logic Component Array (LCA)